In 64-bit design, there will be several places on the data path that needs 64-bit adder, instead
of 32-bit adder. Consequently, for the same micro-architecture, 64-bit design will be at least 20-30%
slower in terms of MHz
You obviously don't have the foggiest notion how fast modern integer ALUs/adders are or how
adder speed varies with word length. The maximum propagation delay of a parallel adder is a
logarithmic function of word size. Most of the work is done in the first few levels of the tree, say
4 to 8 bit sub groups. Depending on the exact implementation details the max prop time of a
64 bit adder might be 10% or so longer than a 32 bit adder in the same technology.
Second of all adder speed is only a part of the logic propagation delay that can define maximum
clock speed. The other components include operand bypass mux delay, register output delay,
and result register setup time. In fact, addition can be done so quickly that the fastest clocked
processor on the planet, the Pentium 4, can effectively perform TWO back to back 32 bit additions
in one clock period (a little over 300 picoseconds). I think it is pretty safe to say that it would be
falling off a log easy to perform *one* 64 bit addition in a clock period and have margin left
over to increase clock rate further (athough no doubt other critical paths would appear).
Just as an aside, when the 64 bit Alpha 21064 appeared it clocked up to 3 times faster than its
32 bit contemporaries made with similar feature size processes.
