Intel Corp (INTC)

[chipguy]

Common wisdom was that SRAMs would never be integrated due to die cost.

Hmmmm? The 68020 had small caches in the era of the 386.

MPU on-die cache was an inevitable result of Moore's law because
it is 1) fully compatible with the most vanilla logic process, and 2)
provided good performance boost at with low design effort and little
effect on the power budget (in that era, prior to leakage becoming
troublesome, growing the cache typically REDUCED device power
because it reduced bus transactions generated from running a given
code sequence).