Advanced Micro Devices Inc (AMD)

[wbmw]

Re: If you think a 512KB 16 way is enough, then a 64KB 1,023 way will have the same cache miss ratio.

Absolutely false.

http://en.wikipedia.org/wiki/CPU_cache


Miss rate versus cache size on the Integer portion of SPEC CPU2000

As you can see, increasing associativity only buys you so much in terms of lower miss rates once you get past 64KB cache sizes. And once you reach 256MB of cache, the difference between a 4-way SA cache and FA cache is zero, at least as far as SPEC_CPU2k goes. If you have a different set of data, please present it; otherwise, your technical inaccuracies are having a negative affect on this board.

Re: K8 with DCA gets an effective L3 using remote L1s and L2s of up to 320 way 9MB.

I can see you added up the cache associativity for both caches (2 for L1I, 2 for L1D, and 16 for L2 = 20) then multiplied it by 16 (were you assuming an 8-way SMP with dual core, perhaps?). However, it's ridiculous to add them up this way. If the processor happened to fill all 16-ways of L2 and had another cache line to the same set, it wouldn't travel across Hypertransport and get stored in another processor's cache. No, the cache would simply evict the least recently used line like it usually does for a 16-way SA cache.

Opterons don't know how to access another processor's cache, and such a design would have no benefit, even if it did exist. The time it takes to leave the processor and query another processor's cache would be nearly as long as a trip to main memory, thus defeating the benefit.

By the way, here is a diagram of K8 cache hierarchy from the same link as above. AMD evidently knows the only appropriate place to put a fully associative cache: right in places where there's only 32 total entries.


Example of hierarchy, the K8