Advanced Micro Devices Inc (AMD)

[chipguy]

It may be slow the way you'd do it. But it can compare all addresses simultaneously in a single cycle, yes, its a bunch of power, but on the same order as a address decode into a memory array. Its the LRU linked list reorder that takes a couple of cycles. Parallelization can shrink cycles in exchange for more power.

1. You have no idea what you are talking about in terms of
implementation and design trade-offs. For example, fully
associative integrated caches generally have very good
low power characteristics (read up on early ARM designs)
but that is about their only good point. Your LRU comment
is completely irrelevent as the replacement policy and its
implementation is a completely orthogonal design issue.

2. As CJ has already said, once you get above about 8
way set associativity increasing associativity further has
very little hit rate benefit and is typically a net performance
loss when you take into account all the negatives design
trade offs from going fully associative.