Advanced Micro Devices Inc (AMD)

[alan81]

ahh--
You are personally more worried about process variation, than intentional variation?
If we take for example the Intel 65nm process which has a minimum channel length of 35nm. When we talk about "minimum" channel length we mean a device that is drawn to be 35nm, as opposed to a device that is drawn to 55nm, or some other number bigger than 35nm. Of course, when you print millions and millions of these over many wafers, many weeks, many fabs, etc... you are going to have variation around the 35nm. I suspect this is what you are really wondering about? The 35nm number is selected such that over all that variation the transistors will be high yielding.

Now, knowing your bias, I suspect you are thinking that Intel hunts through the billions of transistors that they make, looking for the very best one, and then publishing the results on that transistor? Is that your concern, but you just were not willing to state it? Well, when the data is published, it covers many many different transistors generating a curve of data... so such cherry picking is not really going to make much difference. If they pick a device that is say all the way down at 30nm, it is going to have a higher than average drive current, but also a higher than average sub-threshold leakage. Of course, there is also no reason to believe Intel would use a different method than say an IBM when writing an IEDM paper.
--Alan