Intel Corp (INTC)

[Elmer Phud]

Dew -

As Spokeshave said, the pll acts as a clock multiplier so that's where the clock comes from. The internal speed paths limit the frequency so that's where the limit comes from. Why does one device run faster than another? The extra stages in the pipeline have less logic between storage elements so there is less delay between stages and they can run faster.

EP