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Sunday, January 05, 2003 10:44:14 PM
I was just pointing out that when it is poor execution on Intel's part, you use the rather sickly sweet euphemism "capacity constrained", yet when it is poor execution on AMD's part, it is a "disaster".
During the last capacity constraint Intel's volumes were moving to the Willamette die. It was the large die size that constrained Intel's ability to deliver the volume needed to satisfy the market. We don't need to introduce a yield problem to explain the discrepancy. Even with great yields the die was too big. AMD's problems seem to be explained only by poor yield. In the final analysis is there a real difference? I guess it depends on your point of view. Did the process fail AMD or the architects fail Intel? Or maybe Management failed by not realizing the limits of design and process? This is what happens when you push the limit. You find out where it is...
Having said that, the transition to 90nm will be no cakewalk for Intel. They have screwed up a transition in the past, and it is certainly possible that they will do so in the future - especially since this upcoming shrink will involve not just the process shrink, but transition to strained silicon and low-k as well. It is certainly that Intel could be "capacity constrained" again in the future.
Intel can throw money at a problem. AMD can't.
Thanks for your thoughts Spokeshave.
EP
Today AMD may be facing the same problem.
That's because Intel's capacity constraints
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