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Monday, May 16, 2005 3:20:52 PM
(sounds like für Elise
![wink](/images/emoticon03.gif)
http://www-128.ibm.com/developerworks/power/library/pa-nl9-tip.html
Power Architecture Community Newsletter, 16 May 2005: PowerPC processor tips
The IBM® Microelectronics Technical Library has added two new content categories -- one for Blue Gene®/L, and one for the Cell processors.
Porting applications to the IBM eServer Blue Gene/L system solution
....
A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a Cell processor
This ISSCC 2005 session article on static memory, A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a Cell Processor, describes the embedded SRAM in the streaming processor of a Cell chip. This three-page article (one page of description and two of diagrams) details how the synergistic processing element's local store unit handles decoding. (The synergistic processing element is the processor designed to accelerate media and streaming workloads. The local store unit is local memory comprised of several macros that perform load/stores, transactions for DMA, and instruction fetches into an instruction-line buffer.)
The article also addresses how area, power, and yield are as important as performance since the LS occupies one-third of the SPE floor plan (488 Kb, PDF format, presented February 9, 2005).
Thought you might be interested, if you hadn't seen it yet yourself.
Here is the last paper:
http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/372E2BE9229AC34987256FC00074A13A/$file/ISS...
Cheers
Cor
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