Intel Corp (INTC)

[spokeshave]

Elmer: What makes you think SS is comparable high risk?

Well, first off, I never said SS was of comparable risk to SOI. However, even a cursory web search on SS reveals that is is no easy feat, and the added processes in creating SS can significantly increase the chance for defects.

I have been able to find the following as significant factors affecting strained silicon:

1) Strained silicon has a higher dielectric constant and a lower bandgap. This results in increased junction capacitance and leakage. This may be why Intel is choosing to use low-k at the same time.

2) The SiGe substrate for SS has 15 times less thermal conductivity than bulk silicon. This results in self-heating and poorer thermal dissipation. This could be a real problem with the very small die size on 90nm and the associated very small cooling surface area.

3) Strained silicon is more succeptible to dislocations that can result in defects. According to:

http://www.avsusergroups.org/papers/tfug/TFUG_04_2002_Thilderkvist.pdf

the number of dislocations can be greater than 10^5/cm^2.

4) The same link also cited "gate oxidation" as a key issue, though it did not go on to explain.

5) Other key issues cited are: device isolation, process integration difficulties, integration of NMOS and PMOS, enhanced As - P diffusion, parasitic hole channel at strained SiGe/Si interface.

I think you're exaggerating the risk of strained silicon.

With all due respect, I did not even attempt to quantify the risk of SS in even the most abstract terms. How is it then possible that I have exaggerated the risk?

When Intel says they are going to transition to a new process technology I just accept that they will do it.

Regardless of how successful a company is, or how much they spend on R&D, I submit that it is a bit naive to exhibit such blind faith.