Intel Corp (INTC)

[Ali Chen]

Mr.Fud, "You be good now and I let you speak to me."

Thank you very much your highness Test Engineer-III!
I am delighted to have a wonderful opportunity to hear
your deeply insigntful explanations.

I see, you masterfully were able to divide 2.5Gb/s by 10
to ensure the old 1983 IBM encoding scheme to work on
bytes. I would never be able to master such high skills
without your generous help. But trying to comprehend your
following train of thoughts, I am becoming increasingly
confused. You wrote:

"a 250MHz clock would operate the logic that does the 8b10b encoding/decoding. How the bit stream is sampled/generated to ensure correct data at 2.5Gbps is a problem the designers must address and I don't think it needs to be part of the spec."

Besides an impication that a high-flying Test Engineer-III
should care less about woes of some low-level punk designer,
you seem to imply that the 250MHz clock is certainly a part
of the PCI_Express specifications, by the way you are contrasting an
ordinary 250MHz 8b/10b logic to apparently less-challenging
over-gigaherz bit-stream conversion and data scrambling.

Could you please point me to any place in PCI-Express Basic
(or Card) specifications where the 250MHz clock is ever
mentioned?

I am looking forward to listening to more of your lessons about clocks.
Since my screwdriver is always @ posedge, I might have some
difficulties at negedge of your _testful_ insights.

- Ali