Intel Corp (INTC)

[Ali Chen]

"The base clock is 250MHz. You can confirm this by reading the spec"

I do not know what do you mean under "base clock". The PCI
Express specification does not contain such term, not a
single word in he whole 5.7MB pdf.

Since you were speculating about total bandwidth of the
connection, in gigaBITS per second, I had to assume you
must be talking about bit rate on the electrical layer of
the protocol. The spec defines UI - Unit Interval - as
being 400ps, which means that the worst case electrical
signal switches at 1.25GHz rate. All transmitters and
receivers are specified to work up to this frequency.
To implement this signalling, a designer must have at
least 1.25GHz internal clock at his disposal to generate
PCI-Ex data patterns. Therefore I found your "250MHz"
statement quite amusing and misleading.


- Ali

P.S. Tell your buddy Phud to shove the 8b/10b transmission
encoding in his a$$. Please tell him not to try to impress
me with Beacons, QoS, and Root Complexes.