Rambus (RMBS)

[calbiker]

Remember our conversation from last May?

LOL, and who was the first to suggest a different prefetch for the 8 GHz devices?

Calbiker:
"IIRC, there may have been two separate data rate vs. time plots. A 3.2 to 6.4 GHz plot (this is the one we know about) and a 4 to 8 GHz plot. That could mean a different prefetch between the two plots."

http://www.investorshub.com/boards/read_msg.asp?message_id=3145725

Let's leave May '04 behind us, huh?
You got a new May to worry about (not to mention Feb, March, etc.). Ha.

I think you mean the data rate per bit is 4 Gbps.

Yes I did, thanks for the correction.

IBM isn’t using DIMMs.

Looks awful messy to troubleshoot and replace defective memory. Besides having no upgrade path.

With 256MB per node, they have a number of choices. They already use nine 256Mb DDR on a 144 bit bus. (ECC). I think they’re using DDR333. (Spec is 5.6 GBps). The goal is to use commodity DRAM.

I would think their goal is to create a simple memory architecture. There are simpler ways to do it now.

With five XDR 512 Mb x 8-bit chips they could achieve 9.6 GBps using 2.4Gbps devices. That’s 1.7 X the bandwidth using the highest yielding XDR chips.

Why not use the new 4 Gbps devices that Samsung is now producing. Now we'll get 16 GB/s; 2.9 x the bandwidth. Or, they can reduce the device count and save on pins. I think it's way more important to have a simple design.

It also would have a core frequency of only 150 MHz which should reduce system power.

I haven't done an analysis on power savings, but I bet it isn't as mcuh as you think. Sure, the read or write current will be less on a 150 MHz part than the 250 MHz part. But I doubt it will be significantly less. Let's say the faster device has 66% more current during a read operation. With P = V * I, the faster part dissipates 66% more power during reads. But here's the catch, the 250 MHz part is 66% faster. And from an energy point of view (energy = power * time), both parts consume the same amount of energy. Ha.