Advanced Micro Devices Inc (AMD)

[bobs10]

Thanks for the reference. This is the document I remember reading. I've got it book-marked now. I was sure I had read that mirrored-bit had the same number of erase cycles as floating gate, 100k initially. I seem to remember AMD saying they had gotten to the 1M level talked about, but I'm not sure?

One thing I did notice is that the testing was done at the 230nm level so I guess the document is somewhat dated. It's possible that problems were encountered as the die shrank but I don't remember hearing anything about that. As far as I know mirrored bit is now being produced at 110nm, but I'll check.

Anyway, if there really aren't any mirrored bit problems, is the slow uptake due to a long design cycle? More importantly, how much of the flash problems are related to INTC pricing?

I would feel much better if the problems were pricing related rather than product related. If mirrored bit does have a 20 to 30% cost advantage over strata flash then a long term scorched earth pricing policy doesn't seem to make much sense. Boy would I like to know how INTC accounts for flash.