Advanced Micro Devices Inc (AMD)

[chipguy]

The cache thing it adresses could be more sophisticated than just a defect density issue. Somewhat along the line of variations of threshold-voltages where you either cannot make use of an array because these vary more than tolerable within the array, even using redundancy, and even if all cells would basically work at a certain Vth because of variation, or array A can be used at Vth X and array B at Vth Y but you cannot use both arrays together because delta X-Y is beyond spec.

This is complete and utter nonsense.