Intel Corp (INTC)

[SemiconEng]

Semi, can you please take a look at this post here, and comment on the presentations. I would really appreciate hearing from a process expert on this new technology. Thanks.

O.K., just so you know, I'm looking at it from the process side, ie: making the gates, so I would have to take intel's word about the actual performance of the gates themselves. That would be more a Device Engineer.

That being said, I would really LOVE to have lower Poly aspect ratios illustrated on page 10. The comparison of the Source/Drain Tsi Profile Height seems to suggest that the tri-gate would have much lower height requirements. Maintaining profile height, not to mention sidewall uniformity is one of the most difficult parts of the manufacture. One thing I also noticed, is that the tri-gate seems to eliminate the isolation layer present in the Dual Gate. Elimating a Layer reduces costs.

The second thing that caught my eye, was on page 20, where intel states that Multi leg tri-gates increases total current. More current good, less current bad. An oversimplification maybe, but explaining would take pages.

The third advantage I see is the layout width of 0.60 of current transistors. If I'm reading that correctly, this should reduce die size significantly. Could you imagine 2 or 3 meg of cache..... on a P4? With the same die size, and the same power requirements?

One thing I can't help noticing, is there's no discussion of..... Cost. That's an important thing to leave out, and I would have to assume that if it were cheaper, intel would say it. They don't. Overall, it looks like quite a breakthrough, but I have a sneeking suspicion that we'll see it in Itanium, and Xeon, way way before you see it in P4 or Celerons...

JMO

Semi