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chipdesigner

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chipdesigner

Re: chipguy post# 48803

Sunday, 12/05/2004 9:28:18 PM

Sunday, December 05, 2004 9:28:18 PM

Post# of 97573
But would raise serious question about WTF problems AMD
was having with it. Four full mask level respins of a shrink job?


Revisions A, B, C, CG were all 130nm.

D0 is the shrink job (of CG), with minor bug fixes and improvements resulting in 1-3% IPC improvement by some measures.

E0 is the second generation part, probably having the additional metal layers and 2nd generation strain, in addition to adding SSE3, etc.


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