Vitesse Semiconductor (VTSS)

[KlausVT]

Analysis: Carrier Ethernet switch needs
Ron Wilson, Executive Editor - EDN
Thursday 11 February 2010 11:37

http://www.electronicsweekly.com/Articles/2010/02/11/47987/analysis-carrier-ethernet-switch-needs.htm

The explosion of interest in Carrier Ethernet (CE) seems to be at the front of everyone's mind these days.

In case you haven't been following the networking market lately, the basic story is this: Just as wireless service providers and conventional telephone service providers decided to evolve from their legacy switched networks and synchronous rings into Internet-compatible packet networks, they were slammed by a coincidence of three massive trends: the explosion of data traffic in cellular networks, the allure of delivering high-definition television via IP packets to homes, and the rumor of a huge shift toward cloud computing.

The result for both wireless backhaul networks and the wired infrastructure behind all those DSL and cable connections was the same. The providers want a packet-based network with enormous bandwidth—like Enterprise Ethernet—but with all the features these providers had from their legacy networks.

These services include awareness of the service needs of each individual flow through the switch, multicast capability, carrier-class reliability and management functions, and support for precise timing. And of course the carriers want the ability to provide guaranteed quality of service for difficult media types like voice and HD video.

The answer to all these desires, the industry claims, is CE.

The next question is how to implement CE in a way that can be both fast and cheap. Service providers are blowing right past 40-Gbit switches and asking for 100-Gbit capability, but they are severely capital constrained.

The obvious solution is to start with an existing fast enterprise switch and enhance it to provide the additional services. But this runs into problems. If your enterprise switch relies on NPUs, you can simply add to the NPU software, but you will almost certainly run out of processing power long before you get all the new features in, even at low wire speeds. If your switch uses a dedicated ASSP or ASIC, the flexibility won't be there.

Either way, you will have to add an another ASIC or, more likely, an FPGA or two to the design, running up the BOM (bill of materials) cost, the power, and the design time. And, as Vitesse Semiconductor Director of CE Technology Morteza Ghodrat is quick to point out, adding more packet-processing sites to the design means adding more DRAMs and CAMs. Either you put duplicate memory chips around each chip, or you attempt some sort of shared-memory pool with the obvious complications.

That brings Ghodrat to his preferred solution: the three MAC (media-access controller) and switch chips Vitesse is announcing today. He argues that for both architectural and efficiency reasons, it is far better to recognize that all the CE services are related, and that they should be handled from a single architecture rather than distributed across multiple chips.

The new devices are the VSC7460 Jaguar CE Switch, the VSC7462 LynX CE Switch, and the VSC7364 CE-MaX-24 MAC/Switch. As you would expect from the preceding comments, the chips are ASSPs designed to bring the full range of CE functions to high-speed Ethernet switches.

Accordingly, each chip has a service-aware classifier that can manage up to 4k services, each with its own QoS treatment, DE marking, color, policing, OAM (operations, administration, and management), performance monitoring, and timing support via IEEE 1588v2.

The chips provide advanced QoS and MEF (Metro Ethernet Forum) policing based on a shared 32-Mbit buffer. In addition, there are statistics counters, Ethernet OAM for all 4k services, and support for 802.1ag, 802.3, Y.1731, and MEF-16 performance assurances.

The chips differ in CPU and I/O complements. The Jaguar has two 10G XAUI and two 10G VAUI ports on one side and 24 multifunction SGMII/SerDes/100Base-FX ports on the other. The LynX has just half as many of each. Both felines include a 400 MHz MIPS24KEc processor core.

The CE-MaX chip, intended operate in conjunction with an ASIC or FPGA, uses two XAUI ports and a host interface to attach to the other chip, and provides the full 24 SGMIIs plus two more XAUI ports downstream. The CE-MaX does not have an on-chip CPU. All three chips will be in 27x27-mm HSBGA packages, and all are scheduled to sample in the second quarter.

By Ron Wilson, Executive Editor - EDN