Advanced Micro Devices Inc (AMD)

[jhalada]

chipguy,

while the Opteron rarely gets much above 70% ...

... If you build a 4 FP/cycle x86 you might find it hard to run compiled code much above 50% efficiency.

I am not sure why there would need to be a substantial drop. If the code happens to be limited by instruction sequences where only one of the FMUL/FADD type instructions predominates, the lack of efficiency is caused by the fact that only 1 instruction can be issued at one time, and second FMUL/FADD could even improve the efficiency.

Joe