Advanced Micro Devices Inc (AMD)

[jhalada]

wbmw,

I'm not sure I see EPIC as just an instruction set. It's more of an instruction set philosophy. It's not the same as defining different op codes for move, add, and subtract routines ; EPIC actually attempts to make code more parallel through clever use of the compiler.

True, there is that, and there may be less overhead to it doing it in the compiler, rather than through dependency checking and scheduler in the CPU. But the result is similar - some instructions get executed in parallel.

Other than a well designed, low latency cache hierarchy

Which can be implemented on other processors

I think current IPF implementations are rather lame and lag the cutting edge going into designs like Power5; but even so, this so-called lame approach still delivers benchmarks that are compelling. I think a cutting edge IPF micro-architecture would really show some advantages over x86.

Assuming that x86 stays still, true. But as is, the biggest advantage Itanium has over the current x86 implementations is the large cache and 2 FP units. 2nd FP unit on x86 processors would instantly eliminate the SPEC_fp advantage that Itanium currently holds.

I am not sure that adding 2nd FP unit is the highest priority item on the agenda of x86 designers (who are looking at the real world benefits in general purpose computing). It's certainly not a priority for commercial enterprises, though it may be for scientific computing, multimedia and gaming.

Joe