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Re: mmoy post# 46699

Monday, 11/01/2004 7:07:44 PM

Monday, November 01, 2004 7:07:44 PM

Post# of 97775
The cache line is 32 bytes wide. Assuming esi is aligned and the line is not in the cache, the first first read will cause a cache line replacement and the second two reads will be from L1.

The tech docs have information on the load unit but I'm sure it can handle >3 queued load from the address generation unit.

Used to be that the esi load could not be fast decoded and you should force the opcode to be esi+0. Not sure if that is still the case.

Given the shorter code of your second choice that must be faster.
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