Advanced Micro Devices Inc (AMD)

[bobs10]

CJ

Slightly confused. You posted on SI:

The best performance has up to 4 Horus chips connected together in a tetrahedron. Each Horus directly connects to up to 4 Opterons, which might not have any other cHTT connection. Each Horus chip holds a copy of the caches of all of the Opterons in the system. So when an Opteron needs data that is cached, it is one hop to its local Horus and back again. In essence, each Opteron has the same response as it would in a dual system, but with up to 16 sockets. There would be more latency for an uncached memory request, though. Still, this could be on the order of using unregistered PC3200 versus registered PC2100 memory. i.e. the difference could be measured, but...

Me...

The thing I don't understand is if Horus is going to have a copy of all the Opteron caches and it's only 1 hop to the local Horus why does Opteron need any cache itself? More likely why does it need anything other than L1? Especially when considering the need to sync up the caches when there is a change to any of it, and the added burden of finding the most recent data for a read? Just keeping the 4 Horaces in sync seems like challenge enough. It seems like having all the cache in one place and having the processors access it as needed would simplify things greatly.

Of course I still don't understand exactly how multi-threaded programs work. I guess I'm too much of a serial thinker, but it seems like dividing up most programs into tasks that don't all compete for the same resources(data) would be quite a challenge.

I do understand running multiple programs(MFT,MVT), as they have since the 370 days, but true multiple tasking would seem to require a very different way of thinking and a program with very specific needs not to mention a compiler much more advanced than anything available today.