Intel Corp (INTC)

[SemiconEng]

Intel releases 65nm 70 Mbit SRAM chips — Cormac @ 15:16

http://www.digit-life.com/news.html?108089#108089
According to Intel Japan, with an official press release the company released a 65nm 70 Mbit SRAM sample made using strained silicon technology at its Oregon fab. This is not the first such chip, as in November 2003 Intel released 4 Mbit chip (0.57 micrometer2 cell size).
The novelty has the same cell size and over 0.5 billion transistors. Transistors have 35nm gates that´s about 1/3 smaller than that of a 90nm crystal. Besides, according to the press release, leakage currents were reduced by 4 times.
The press release stresses the reduced power consumption made possible by sleep transistors feature that disables unused circuits.
Volume production of 65nm chips is expected in H1 2005 at fabs in Oregon, Arizona and then in Ireland. According to Intel, the company will try to reduce production capital expenses by using existing litho tools (248nm and 193nm).


* Sounds like some sort of Phase Shift Litho exposure will need to be done, in order to reuse those Litho tools. It works, but reduces throughput significantly, so you need more Litho tools to meet the capacity requirements. In this case, it probably is still cost effective, because there are probably quite a few of those 248nm and maybe some 193nm reuse Litho Steppers available from the demolition of the Fab12 equipment. Since those have already been fully depreciated, can anybody say..... Free tools?