Advanced Micro Devices Inc (AMD)

[pgerassi]

Chipguy:

Look at this for P3 stages. I do not agree with the author on how he classifies P4. But does have information on P3, P4, Itanium, Athlon and Hammer (K8): http://www.ugrad.cs.ubc.ca/~cs318/notes2004/Lec20-Pentium-Athlon-318-04-6p.pdf

Here to is the fact that P3 has 10 stages. Here the execute portion doing the same task, executing uops, is 5:20. From x86 to retirement, P4 has 28 stages, 20 in the uop execution pipeline and 8 in the x86 decode to uop pipeline. On P3, it is 10 stages, count them. On Athlon (K7) has 11 stages. Hammer (K8) has 12 stages and Itanium has 10 stages.

Here is another source: http://www.planethardware.com/features/cpu/p4_1700/index2.shtml

From Intel itself: http://www.intel.com/cd/ids/developer/asmo-na/eng/microprocessors/ia32/pentium4/optimization/44015.h...
and here: http://www.intel.com/labs/features/mi06031.htm
and here: http://www.intel.com/design/PentiumII/manuals/24350201.pdf

So you are wrong about the P3 having more than 10 stages. The P3 came out in 1999. I suspect that the design changed greatly from 1995 when truly implemented. So did Itanium, Athlon, Hammer and many others. Of course floating point had more stages (15 in most documents I have read) and things like integer divide are actually a series of uops (latency is 32 cycles). But most look at things like AND and OR that take 1 cycle to execute and these only take 10 stages.

Intel does not want to reveal how many stages Banias and Dothan have. The range speculated is from 10 to 14 for integer operations. But, with no definite size confirmed by Intel, it is very hard to choose one.

Pete