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TSMC's research chief mulls next-gen process knots
By EE Times
May 17, 2002 (8:56 AM)
URL: http://www.eetimes.com/story/OEG20020517S0044
About this time last year, Taiwan Semiconductor Manufacturing Co. closed a deal with a far-reaching impact on its position in the semiconductor industry: It wooed the influential Chen-ming Hu away from the University of California at Berkeley. As chief technology officer, Hu juggles the process headaches of tomorrow, overseeing 30 TSMC engineers whose mission is to come up with ways around the obstacles that await designers at the 65-nanometer node and beyond. In an exclusive interview with EE Times Taiwan bureau chief Mike Clendenin, Hu shared his thoughts on the process challenges, the economic hurdles of scaling and the markets on which the world's top foundry will build its future.

EE Times: During a recent TSMC seminar, you went to great lengths to explain that the limits to technology are far off. But let's look at it in another way: Could one argue that the economic challenges of scaling may be the more difficult obstacle to overcome in the near future, especially for small companies with low volumes?

Chen-ming Hu: It's clear that if there is no economic benefit to scaling, then it isn't going to happen. It's interesting that the last few generations of scaling have continued to reduce the cost for the manufacturers and for the buyers of chips, so if there is a limit to scaling as a result of cost then we are not there yet. Are we going to get there sometime? Right now we cannot tell.

Often the economic discussion is phrased in terms of the number of dollars it takes to build a fab. . . . In the early '90s, the concern in the industry was how many companies could afford to build billion-dollar fabs. But not long after that, in the mid-'90s, the concern changed 180 degrees: There were too many of those billion-dollar, 8-inch fabs being built. There was a glut that created a price depression. That was a good lesson to learn.

As long as this trend of building larger fabs-using more-advanced technology-continues to reduce overall cost, then the investment will be there to build these fabs. Today, the cost has increased to $3 billion to $4 billion, and that still has not stopped companies from investing.

In the future, the upper limit of the size of the fab will probably be determined by risk management. It will probably be better to build two $5 billion fabs instead of one $10 billion fab. So far, economic concerns, in terms of return on investment, have not shown that the path we're on is not the right path.

EET: Can you now address the guys who need to do smaller volumes but still need to deal with what will become multimillion-dollar mask sets?

Hu: It is a problem. The rising cost of masks is becoming an increasing concern to the smaller users of these advanced technologies. Regardless of the volume, the user can always benefit from the reduced cost per die. However, the nonrecurring-engineering cost is something that will be hard for small-volume users to bear.

The Cyber Shuttle program [which places multiple ICs on a single wafer for prototyping] has made it a lot easier and economical for small-volume users to do prototyping. Unfortunately, at this point, Cyber Shuttle is not yet a solution for production mask costs.

There are some innovative ways that we are investigating to leverage the Cyber Shuttle infrastructure to make small-volume production. We are not ready to talk about the specifics, but there are ways to implement it. [No time line for introduction has been fixed.]

The longer-term solution will have to come from technology again. There is maskless lithography technology that is not necessarily very far off. Perhaps in five or six years we could be looking at maskless lithography, and that would be a relief for small-volume production and prototyping.

EET: There is a handful of options being investigated for patterning wafers, such as electron-beam lithography or extreme-ultraviolet lithography. In the future, how do you see these competing candidates interacting?

Hu: I suppose you can say these compete, but sometimes they may complement each other because some of the layers can be done more easily with one technology while others can more easily be done with other technology. So it's likely that we will be using multiple lithography technologies in the future depending on the layers.

We are also looking at the continuing option of optical lithography, such as 157 nanometer. All of these are being investigated, partly because we think a combination of them may be used.

EET: As you look at the 65-nanometer node and beyond, what worries you most in developing process technology?

Hu: It is difficult to order the challenges in terms of difficulty. Each of several problems really looks difficult, and until we solve them and look backward, we can't say with any degree of confidence that one is more difficult than the other.

Lithography is certainly a challenge. Reliability and maintenance of high yield continue to be a challenge. Leakage current, both through the gate and through source and drain, is a challenge. And finally, the rising power dissipation is a challenge.

One common characteristic of these challenges is that while they all present very difficult engineering problems, fundamental physics does not tell us that we are nearing the limit.

EET: You mention gate leakage. Right now there are two options out there for addressing this problem: high-k gate dielectrics and double-gated structures. How do you foresee these two solutions being implemented?

Hu: Fundamentally these two approaches solve two somewhat different problems. The high-k dielectric solves the problem of leakage between the gate electrode and the channel or source or drain. The double-gate structure solves the problem of leakage current between drain and source. . . . At some point, we will need both of these things to take us far.

As to the question of which will be taken to manufacturing first, if I had to venture a guess I would think high-k dielectric will be brought to the manufacturing floor first, partly because gate leakage appears to be the more urgent problem.

EET: A few have suggested otherwise-that double-gate could come first.

Hu: I'm not surprised to hear that. These are complementary things; whichever can be brought to practice first, will be. High-k technology is the one that has been researched more thoroughly and, indeed, it has proven to be more difficult than most people expected.

In contrast, the double-gate structure has not received as much R&D effort from as wide a community, so from that point of view, if you are an optimist, then you could say that the double-gate has more of an opportunity of succeeding just because not the same amount of effort has been put into it. If you are a pessimist, you might say that once we put more effort into it we might notice some more difficulties.

But both are attractive, and eventually both will need to be done.

EET: From your research at TSMC, what is the most meaningful challenge in working with high-k?

Hu: It is the quality of the interface-more specifically, the mobility, the transport properties of the electrons and holes at that interface. The interface quality between high-k and silicon is still not as good as the quality of the silicon dioxide interface that we have come to expect as being the norm. It is a tough benchmark to measure any new technology against.

EET: Are you leaning more toward hafnium oxide or zirconium oxide as the high-k material of choice?

Hu: We are not certain. The option is still wide open at this time.

EET: What roles will silicon-on-insulator and strained silicon have in the industry?

Hu: The prevalence of SOI in the future IC industry is still an unanswered question. What Intel decides to do with this technology will have a large impact on the degree of acceptance of the technology by the industry.

It is likely that for a fairly long time, SOI and bulk technology will coexist. It is also likely, over this period of coexistence, that bulk technology will be the mainstream and that SOI will hold the minority market share while slowly gaining [on bulk technology].

This coexistence will likely be very long. So it is prudent for TSMC to develop SOI technology and be prepared to meet the demand for the technology when the market shows up.

EET: Will there be a real need at the foundries for this if you're not producing the high-performance transistors used in multigigahertz processors?

Hu: Indeed, we don't see a lot of interest in SOI. Most of our customers are happy with the 0.13-micron technology, and they are starting to look at design for 90 nm, so there is still a lot of opportunity for customers to get better product performance from the available bulk technologies.

EET: Could you say the same thing about strained silicon at the foundries?

Hu: Strained silicon could be more prevalent than SOI technology in the future. It depends on the cost of the strained-silicon substrate. If a low-cost technology can be developed, then the barrier for entry is actually quite low.

Strained silicon is more of an unknown than SOI at this point so it is difficult to predict the cost of a strained-silicon substrate, but there is the potential that some flavor of strained silicon could be a widely used enhancement of the IC technology.

EET: Foundries have been catching up in process technology with the likes of Intel, but at the end of the day the foundries are said to have a more plain-vanilla process because you have to satisfy so many diverse customers. With that in mind, do you ever see TSMC's catching up to Intel in raw transistor performance-or to the likes of IBM, which is usually at the forefront of introducing new materials?

Hu: IBM and Intel are longstanding technology leaders in the industry. I do not think that TSMC necessarily wants to surpass those leaders. We would be happy just to achieve parity and allow our customers to achieve comparable product performance.

The strength of the foundry industry is flexibility and the breadth of applications that it can serve.

EET: As things become more difficult in achieving integration for system-on-chip designs, do you foresee fabless companies and foundries coming closer together?

Hu: As the technology gets more complex, one would think there would be a greater need for communication between designers and the foundry companies. At the same time, the method of communication has been improving, such that I do not see more visits from the fabless companies to TSMC.

One example of the improvement in the method of communication is the e-business initiative that TSMC has undertaken. Designers can now work with a TSMC engineer although the two parties are separated by the Pacific Ocean. They can look at the same design layout or yield data in real-time. They can do virtual testing of the product.

EET: What is TSMC's interest in getting into more sophisticated MEMS [microelectromechanical systems] production?

Hu: TSMC is doing research and investing in future markets. We are producing MEMS products today and we would be interested in taking on more MEMS business, provided the technology that's required is in tune with our basic semiconductor manufacturing technology. . . . I see CMOS technology as a platform on which to put optical devices, MEMS or even carbon nanotubes, just as we are starting to put silicon germanium on it for strained silicon today.