Friday, May 17, 2002 4:26:54 PM
While I share concerns regarding TSMC's ramp of .13 micron chips, I don't think a second source is appropriate at this point. I found it interesting that cadpdvr emphasized M Perry's comments that there exists a special relationship between the company and TSMC. I think this is very real, and, really, is our ace in the hole. David Tai, a TMTA board member, was part of the team that launched TSMC (David wrote the business plan if I recall), and I am sure remains very active in that company. I believe that TSMC has made a firm commitment to TMTA to ramp to a certain minimum volume of chips per week (I believe that this is 10,000) and TSMC has made it a corporate priority to get there. The recent increase in capex (to US$2.5B in '02) by the TSMC board was a strong sign of this I thought, as well as a sign that TSMC intends to be THE contract foundry.
While we can be frustrated by what appears to be strong demand for Crusoes and slowly increasing supply, the bottom line is that we have a state of the art foundry aggressively ramping up production to meet our needs, with an apparent commitment in the midterm to being able to produce whatever we can sell. Not a bad situation all in all.
All the chip builders seem to be having problems with moving to 300mm wafers and .13 micron spacing, even Intel (having major leakage problems?). I very much doubt that UMC is able to produce acceptable .13 micron product at this point. If they had this capability, AMD would be the first buyer in line.
my US$0.02 wsh
PS: Bird, do you know how many TM5800s can be produced from a 300mm wafer, assuming a high yield?
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