Intel Corp (INTC)

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Another ISSCC 2009 Abstract

3.4 Dynamic Frequency-Switching Clock System on A Quad-Core Itanium® Processor
3:15 PM

A. Allen, J. Desai, D. Mulvihill, F. Verdico, F. Anderson
Intel, Fort Collins, CO

The clock system for a 700mm2 65nm quad-core Itanium® processor has a cascaded PLL architecture and enables dynamic frequency switching with a single-cycle switch penalty and minimal di/dt impact, which minimizes power-supply disturbance. This allows
frequency-power optimization without stopping the clock.