Intel Corp (INTC)

[Andy Grave]

Sigh. In the interest of everyone else here, to make you
go away I'll answer you. Go read my orginal post you took
exception to:

I read your original post and you simply are wrong. The minimum channel length for Intel's 45nm process is 35nm as they state in the IEDM presentation. I ask yet again for you to provide the references to the two PDFs you claim show a 25nm minimum gate length. Your claim that the 10nm of "insulating barrier material" reduces the gate length to 25nm is ridiculous. How do you explain the rolloff curves which do not extend below 30nm?

Andy Grave