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Re: Elmer Phud post# 86260

Friday, 11/21/2008 8:51:22 PM

Friday, November 21, 2008 8:51:22 PM

Post# of 97573
Ephud:

Lets look at each submission instead. Results come first and then base below. On my lists, where I don't display base, ridiculous as base doesn't mean much especially given the way Intel's SPEC special icc and ifc compilers act (although other OEM built compilers may have the same tendencies), the result scores mean more. Unless you use gcc or other third party compiler for both, base is typically poor to compare systems using normal developer usages of compilers (compile using make, test application, fix source and make scripts, do again until tests pass).

As for the score, the SPECint_rate2006 score of 125(117) score of the 3.2Ghz i7 965 is worse than the 2P 2.7GHz Shanghai score of 136(113). Using the same compiler as the third party one for Shanghai of Pathscale's v3.2 and Portland Group Inc's v7.3, likely the base and result scores would be wider for Intel. I also notice that Intel's submission was all 32 bit code whereas AMD's was mostly 64 bit. The Pathscale and PGI compilers are far more widely used than Intel's. And wrt to Microsoft, GNU (Gcc and variants), HP, Sun and IBM compilers, Intel compiler's share is tiny.

Of course that was desktop memory without ECC for i7 and over one day, some 12 bit changes during reads occurred whereas the AMD submission using 32GB likely won't have any unfixed bit errors over years of operation (fer more certainly any bit error that were not found). Phenom II will likely have higher clock and faster PC2-8500 CL3 memory and no need of cache coherency as the 2P had to endure in a long tested OEM platform.

BTW, given that no 2P or 4P i7 scores were submitted to SPEC, it looks like Intel is assuming 2P Nehalem won't arrive for at least 6 months. That puts it into late Q2/09, a full quarter beyond what the Intel boosters would like. Also I notice that a good deal of the 77 errata on i7 stepping C0, involve data corruption in some way or lock ups, with a possible BIOS based "workaround" for some of them! Perhaps they are waiting for a new stepping to fix these nasty errata. Given how BIOS workarounds usually decrease substantially performance (one only need to look at Barcelona stepping B2 to see how), this reported 160 in SPECfp_rate2006 could vastly overstate the performance of a production CPU based system.

OTOH, with HT3.x (possibly DDR3) with dual HT3.x links between the two CPUs and the clock boost of the Opteron SE CPUs, the Opteron scores may get a substantial boost as well.

As always, we need to wait and see.

Pete
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