Ricoh Integrates Cadence Encounter Platform for Digital IC Design
Saturday , July 26, 2008 00:13ET
Cadence Design Systems, a provider of global design solutions, announced that Ricoh Company has started to adopt Cadence Encounter RTL-to-GDSII system for digital IC design.
"As a consumer electronics industry leader, Ricoh is focused on getting innovative products to market first," said Kazunobu Sugaya, manager, Design Engineering Section, Imaging System LSI Development Center, Electronic Devices Company, Ricoh. "Using the Cadence Encounter digital IC design flow, we are able to gain greater productivity and faster time to market for digital IC design. This is critical as we drive next-generation, large-scale complex chips targeted for advanced process technologies."
After the digital IC evaluation, a new design flow was developed based on the holistic Cadence Encounter RTL to GDSII system, the company said. This logic design and physical implementation flow includes Encounter RTL Compiler synthesis, Conformal Equivalence Checker, First Encounter Silicon Virtual Prototyping and SOC Encounter. Ricoh said it is now starting to evaluate the Si2 Common Power Format (CPF)-based Cadence Low-Power Solution, which they expect would support the Ricoh 'Eco Management' initiative to reduce power consumption in electronic devices.
"Ricoh's decision to upgrade their longstanding digital implementation solution with the Cadence Encounter Platform is a strong endorsement of our recent aggressive technology advancements and our ability to provide differentiated solutions for low-power and advanced node designs," said Chi-Ping Hsu, corporate VP, IC Digital and Power Forward. "We are confident with our focused advanced technology developments to continue the Cadence leadership in advanced node and low power designs."
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