Intel Corp (INTC)

[SemiconEng]

Fab engineers save Intel's butt

And AMD always second best

http://www.theinquirer.net/?article=15891
I mentioned in January that the target specs on the next generation (Tejas) would be 1000 MHz bus (or 1066 depending on divisor) with 2 MB of cache. Since the departing designers do not need to keep these things in their bag of tricks and as they are relatively simple to implement they went ahead and added these already developed features to the production database for the Prescott, leaving the engineers at the fab then capable of generating masks which incorporate these features.....
Since it costs next to nothing to carry the DP and MP circuitry in the desktop chip look for Intel to simplify the Prescott/Nocona/Potomac lines to two chip variants, with and without L3 cache and then use bond out options to select what it can do ala the Opteron.....


*** So..... despite all the reported "roadmap turmoil", It appears that in this case, Manufacturing Process Engineering rides to the rescue, and saves the day..... Again. Speaking for PE's everywhere, all I can say is.....

You're Welcome :-]