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Friday, 05/07/2004 12:29:50 PM

Friday, May 07, 2004 12:29:50 PM

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Intel's 'causal learning algorithm' to reduce IC test costs


http://tinyurl.com/3c9lx
SANTA CLARA, Calif. — Looking to reduce the soaring costs of IC test, Intel Corp. hopes to leverage its "causal learning algorithm" technology for wafer sorting applications in the fab.

Intel is looking to deploy its machine learning technology within standard automatic test equipment (ATE) to predict chip failures in the wafer sorting process, said Gary Bradski, manager of the machine learning group within the Systems Technology Lab at Intel.

The technology is expected to provide a major "cost savings on test algorithms," Bradski said. In theory, the technology could detect 70 percent of the errors in 10 percent of the die in wafer sort, he said in an interview at a press and analyst event at the company's headquarters on Wednesday (May 5).

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