Advanced Micro Devices Inc (AMD)

[kpf]

Paul

I wonder if they plan on going to 11 metal layers during K8 generation, or if that's reserved for K9?

I understand its needed for the 200mm process already.

And how much time and yield issues will it add?

Timewise, it depends on if they are prepared for this in the expansion space of Fab30. If yes, nothing, if no, quite a bit, up to 10% percent waferstarts next year.

And yes, it will definitely increase yield-losses. But it would be misleading to say its like ten percent or any other linear figure. Adding 2 to the current exponent over the average line yields gives the better picture.

For an whole picture what adding two layers really means, take time into account: It will take roughly the same time as it took from Thoroughbred A to Thoroughbred B until 90nm will be scale better than 130nm does. But to prevent from any misunderstandings, the results wont be as they were then:
1. 130nm is far from being at the end of its cycle, it will still scale for a while.
2. If AMD ommunicates additional layers many months before shipping initial nine IC-layer volumes, they have been starting to work on it already. Initial 11-IC-layer products can be expected in H1 2005.

What exactly does "active pilot" mode mean?

As far as I understand, pilot production is running initial wafers on production schedules (instead of engineering wafers as rocket-lots)

K.