Advanced Micro Devices Inc (AMD)

[VBG]

I'm confused. I thought cache benefited more from a shrink than logic. So shouldn't we expect a design that is mostly logic and little cache like Barc to shrink poorly relative to a design with more cache %?

Regardless this doesn't seem very promising from a cost standpoint for AMD. I would expect that using immersion @ 45nm would provide more benefits.

Has AMD divulged any details like contacted gate pitch for 45nm? Has AMD announced any specific improvements in Shanghai that might account for the extra die area?

Maybe Hans will do a detailed die plot analysis soon....