Intel Corp (INTC)

[VBG]

Memory latency improvements with Nehalem

The thing I found confusing was the system diagrams on the first page that show the memory directly connected to the processor for 1P/2P/4P systems contrasted with the "Tylersburg HEDT" system diagram shown on the second page which have the memory connected to the chipset.

Can we infer that all Nehalem flavors have a IMC?
Is there a redundant IMC in Tylersburg that is only used in certain configurations? Won't this high-end desktop configuration suffer from a memory latency penalty v.s other configurations?

-VBG

Edit: According to HKEPC slides at least, Bloomfield will support 3 channels of DDR3.