I think the metric for mainstream parts is performance per unit of die size. IPF has to at least be somewhat competitive in this metric for broad adoption, don't you think?
First all the cost that is important to the real customer is
the system cost, not one of the components. In the server
market that IPF currently resides in, IPF processors go
up against CPUs like POWER4+ and USIII and US-IV
which require big off-CPU caches (128 MB per MCM, 8
or 16 MB per chip respectively). With the exception of the
IBM x455, all IPF systems ship with no cache except that
which is on the I2's die. That is a radical departure
from the last 15 years of server design and contributes
to system level cost savings.
Looking at microprocessor die size itself, you have to
remember that IC cost goes up with size for two different
reasons. The first is you get fewer chips per wafer and
it costs the same to produce a wafer with lots of little
parts as a wafer with a few big parts. The second, and
often more important reason is there is a greater chance
of a killer point defect in a large chip than in a small
chip. But some chip elements like cache can be designed
with redundant elements that can be substituted for areas
rendered useless from a point defect. With proper design
a 400 mm2 processor that's 75% cache by area need not
have worse defectivity yield than a 150 mm2 chip that is
33% cache by area. Let's call the portion of a chip that is
not redundancy protected the "critical area" since defects
in that area are almost always fatal while defects in redun-
dancy protected regions are almost always fixable.
The 374 mm2 Madison I2 has a somewhat smaller critical
area than a 131 mm2 Northwood P4. Although a Madison
will still cost about 3x more to make than a P4 (say $120 vs
$40) simply from wafer area usage, it is not the 5x or 10x
more to make if it was simply a scaled up x86 design like
P4 that is over 75% critical area.
