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Tuesday, February 24, 2004 11:20:22 PM
--Alan
---Most likely, the 3.0 and future speeds are the restepping that intel had to delay introduction of Prescott for, which was widly reported, and the 2.4GHz are most likely earlier Prescott steppings that didn't bin out. Here's how a hypothetical scenerio might have played out.
Yield Engineer: OK, the initial Stepping isn't meeting speed bins, the restepping is in-line, but what are we going to do with all these lower speed chips
Marketing Guy: Can't introduce those low speed chips as Prescott, that would be an embarassment, we have to delay the introduction until the restepping is ready.
Manager: We can't throw away all those chips, they cost a fortune, store them somewhere, and we'll decide what to do with them later...
Time passes..... Say.... Oh about the same amount of time Prescott was delayed......
Yield Engineer: The restepping looks good, still going to be hot, but the meat of the bell curve is around 3.0.... with the edge of the curve around 2.8-3.2 with limited 3.4 quantities. Should we delay again?
Marketing Guy: GO GO GO GO GO GO GO....
Manager: Delayed once already...... How soon will we see some improvement in the Top Speed bins?
Yield Engineer: Well we have the most superior, wonderful marvelous, smart, educated....... and not to mention, good looking, Device and Process Improvement Engineers, they'll have the solutions in no time.
Manager: OK, here's what we do, introduce the restepping (Marketing Guy Dances), Get the Device and Process Engineers into Task force on the improvements, and let's brainstorm what to do with those first steppings.
Device Engineer: Well, if we fuse some of the cache.... Like we did before on previous Px Chips..... we could sell them as Prescott Celerons.....
Manager: BRILLIANT!
Marketing Guy: BRILLIANT!
---Just a thought..... Far fetched huh? But it does fit, doesn't it?
![smile](/images/emoticon01.gif)
Semi
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