Advanced Micro Devices Inc (AMD)

[dougSF30]

Speculation on Nocona performance from SI:

(from pgerassi)

http://www.siliconinvestor.com/stocktalk/msg.gsp?msgid=19819331

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IA32e as implemented on Prescott and Nacona allows only 64GB at most and typically less than that (from comments in the IA32e guide). That means that Opteron can use more physical memory. Since Opteron now can have 32GB per CPU, 4P Opterons can have twice the memory and 8Ps have four times the memory of 4/8P Xeons. Current desktop chipsets for Prescott do not allow for more than 4GB, thus any Opteron or A64 FX based MB can have more memory. Even 754 based Athlon 64s can have more memory (nothing stopping use of 2 or 3 4GB registered memory DIMMs) than Prescotts.

Second, unless Intel built the hardware assists for the same breaks in address mapping (unlikely but, possible), 64 bit to 36 bit physical translations probably include a 1, 2, 3 or 4 cycle penalty each. This will slow down all memory based references even to L1 and L2. This may be a significant reason why the first spins may be much slower and why Intel doesn't want them benched in any way. By Q4-4 or Q1-5 they may be able to remove this latency and get a major speed boost.

Lastly, the microcode additions will further slow down decoding plus make the decoded traces longer perhaps by as much as 50% (corner cases may see up to 300% increase). This will probably take a new core to fix and that is 18 to 24 months down the road. This also will slow down 64 bit programs so that the Prescott and Nacona will run 1/2 to 1/3 the IPC of K8. This will help Itanium for a while but, K8 will force Xeon 64 to be much better or die. And with Xeon revenue bering much greater than Itanium, Intel can not afford for Xeon to go away.

Pete