Advanced Micro Devices Inc (AMD)

[j3pflynn]

mas et al - That part I knew. What I don't recall is the width of the memory controller-to-crossbar bus, or for that matter the throughput/configuration of the crossbar to the rest of the core. I guess what I'm wondering is what the max theoretical throughput is, although that's kind of hard to nail down with changing frequencies, isn't it?
Paul