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Post# of 97827
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j3pflynn

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j3pflynn

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Tuesday, 01/13/2004 4:53:41 PM

Tuesday, January 13, 2004 4:53:41 PM

Post# of 97827
Anyone know offhand what the theoretical peak bandwidth memory controller to core is in K8? Is it more than dual channel PC3200 DDR(1) can provide?

If so, I expect that every bit of bandwidth and latency advantage that 939 can offer will be used; unlike nForce2 where the EV6 "bus" was already saturated. Dual channel PC3200 matched P4 closely, though, but didn't seem to pay off like one might expect.

Time to start digging, I believe.

Paul

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