Advanced Micro Devices Inc (AMD)

[SemiconEng]

---Let's assume that's true for a moment. C1 Stepping sample to vendor in December to me, means Intel would have had mid-line functionality data in mid-November on whatever C1 Stepping material was in line.(6 weeks prior, according to the sites 2-3 month production estimate noted below), at which time, they could have started the C1 Volume Wafer Starts. It's actually about 10 weeks now, but I digress. How many wafers did intel start with those samples by the way? Don't know.

Shoot, ran out of re-edit time. The reason I think that intel could have Theoretically done risk starts based on Mid Line data, without waiting for End Of line data, is because there is usually in most semiconductor manufacturing, including flash, a Post Transistor Creation Electrical Test of the Transistors, Mid-Line, before the Metal Layers are laid down. Makes sense, eh? It is also assuming that the chip needed a redesign, and the redesign that was needed was in the Transistors, not the Metal Layer. I know..... Lots of assumptions, and guesses, but I'm trying to at least make them based on some educated semiconductor manufacturing thinking.

Not much, I know.



Semi