Rambus (RMBS)

[cordob]

So eventually we may finally see a DDR memory controller off a Hypertransport bus (something I predicted years ago). Imagine how much memory you can put on that at lareg distances:)
Different hierarchies of memory as with L1, L2, L3 cache, some connected to the memory controller and some to the HT controller.

Or what about memory chips with built in HT support?


I know already what you are going to say, Cal:)

Cheers
Cor