HP, Actel back reconfigurable SoC contender
By Peter Clarke
EE Times
(07/30/01, 2:42 p.m. EST)
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LONDON — A startup spun off the U.K. branch of Hewlett-Packard Laboratories is commercializing a reconfigurable ALU technology that poses a significant new option in a growing field of reconfigurable and embedded DSP alternatives.
Elixent Ltd. (Bristol, England) is one of many contenders aiming to set the reconfigurable system-on-chip market alight. Already, FPGA vendors are bringing diffused processor cores onto their reconfigurable chips for improved areal density, and ASIC vendors are seeking licenses to FPGA architectures to add reconfigurability options to their designs.
"The advent of reconfigurable intellectual-property cores tuned for computation provides an important new platform for deploying embedded DSP in SoC devices," said analyst Will Strauss, president of consulting firm Forward Concepts (Tempe, Ariz.). "I believe this is a major trend in the development of embedded DSP over the next few years."
The Elixent ALU array shows similarities to a number of parallel-processing architectures announced in recent months, although company executives stressed that theirs is not a multiprocessing architecture.
Pact GmbH (Munich, Germany) is offering an array-of-CPUs architecture for licensing. The Pact architecture, based on a sea of 32-bit RISC processors, is an extremely high-performance option but is also likely to be a less-nimble solution as a functional accelerator.
Xilinx Inc. (San Jose, Calif.) has launched its own XtremeDSP architecture, which could provide up to 192 18 x 18-bit single-cycle multipliers, associated registers, up to 3.5 Mbits of dual-port RAM and up to 10 million configurable logic gates on one chip.
It is being pitched squarely at the configurable and reconfigurable markets but thus far has been offered only as a standalone Virtex FPGA, not as a licensable technology for inclusion in systems-on-chip.
Elixent, by contrast, plans to offer its array technology as licensable IP for inclusion in system-chip designs. The sea-of-ALUs architecture, investigated at the U.K. laboratories during the second half of the 1990s, is being pitched as an additional on-chip block that could help configure system chips to suit multiple applications. Executives said they plan to develop expertise in application-specific algorithms and to map those algorithms to the Elixent array, with the first such application likely to be in digital imaging.
The array technology would afford system chips, which would probably already include a pro-cessor and a DSP core, additional configurability and in-system reconfigurability, much as FPGA technology is being used to bolster some ASIC designs.
Indeed, Elixent's technology has similarities to the field-programmable gate array. It can be programmed in the field and includes both nearest-neighbor and longer-distance wiring that is configured through SRAM-based switching blocks.
But instead of linking a Manhattan array of configurable logic blocks, as in FPGAs, the Elixent array comprises a chess board pattern of 4-bit software-programmable ALUs, together with blocks of embedded RAM. The ALUs cascade flexibly, so that 8-, 16- or 32-bit data can be processed. For an array of 16 ALUs operating at 100 MHz, the theoretical maximum performance is 400 million 16-bit operations per second.
Software assist
To help OEMs programming the array, the company will provide place and route software that can create a configuration file from a netlist format. Elixent expects C language, Verilog and VHDL design entry to be supported, either by its own tools or by mainstream tools from EDA vendors.
"The benefits of reconfigurability, including time-to-market, feature flexibility, and the optimization of cost, size and power consumption, will be easily accessible to chip designers using Elixent's tools and products," said chief executive officer Kenn Lamb.
But it is the ability to go beyond FPGA technology and have software-mediated, algorithmic acceleration in reasonably efficient silicon area that is likely to appeal most to OEMs.
"There are examples [where functions are] four or five times less dense in Elixent than standard-cell ASICs but four or five times more [area] efficient than in a typical FPGA, although it is very application-dependent," said Alan Marshall, chief technology officer of Elixent.
The company is evaluating deployment of the Elixent array on 0.18-micron CMOS technology. "We think an array of 128 ALUs might be a useful number, in a square configuration," Marshall said. "We are aiming at a density of 100 ALUs per square millimeter. We could occupy five or 10 square millimeters on the SoC, depending on what the customer requires."
Marshall called the architecture well-suited to pipelined dataflow processing. The array is register-rich, with three 4-bit registers per ALU; that, together with the embedded RAM, helps the array minimize the bandwidth used on an on-chip bus, he said.
"We can store the intermediate results, so we just take data in off the bus and put results back," Marshall said. "It suits the use of the array for accelerator blocks."
The Elixent array also offers fast reconfiguration times and the ability to do partial reconfiguration, he said. "The compact nature of the configuration data — 100 bits per 4-bit ALU — means we can reconfigure in the tens of microseconds, or an order of magnitude less than typical FPGA technology."
The partial reconfiguration of just a few ALUs could reduce times still further, he said, although the array does not support "hot" reconfiguration, meaning that the whole array would have to suspend programming for a number of clock cycles while the reconfiguration is done.
"If it's a continuous data application, you do need buffering to cope with that," said Marshall.
Finally, the ALU subarrays and the complete array can be switched off to save power while the piece of equipment driven by the SoC is in a different mode of operation.
Actel investment
Actel Corp., which has taken a stake in Elixent as a cash investor, sees a complementary role for licensable FPGA and field-programmable ALU arrays.
"Elixent is developing competitive reconfigurable cores for embedded DSP computation that complement Actel's Vari-core embedded-FPGA offering," said Yankin Tanurhan, senior director of Actel's embedded-FPGA effort. "We believe Elixent's mix of assets and technology is highly synergistic with Actel's road map."
"Elixent's technology can enable families of high-volume products to be developed around affordable and scalable processing architecture," said Hoyle Curtis, director of strategic alliances at HP Laboratories.
Elixent's Lamb said the company will likely develop standalone devices for development systems and for sampling to potential companies. But he would not predict whether the company will make such devices more widely available as standard parts.
Elixent has received $14 million in backing from HP, Actel and venture-capital firm 3i Ltd. Most of the startup's senior management hails from the HP labs.
