I never claimed that the OOO registers were accessible to the programmer. The fact is, it is a BLESSING that 400+ 64-bit registers are hidden, and instead used very efficiently for out-of-order and simultaneous execution.
Much more efficiently than you or any Intel compiler could possibly use your vaunted 128or 256 registers. Because the compiler cannot see anything about the dynamic execution of a program or know what is in the registers when a subroutine is called from diverse places in a huge programming project.
I am amazed that you are ready to quickly dismiss the fact that Intel proved over and over that OOO+few registers is more efficient than no OOO+many registers.
In fact, I'll go out on a limb and predict that Intel will attempt to add OOO to Itanium 3 to correct those situations where the compiler just couldn't find 3 things to do on every clock cycle. It'll be tough to have many copies of all those registers, but Intel doesn't care how much extra silicon it will require.
...those OOO regsiters are merely duplicates of the Athlon 64/Opteron 16 registers
'Duplicates' is the wrong word since they don't contain the same thing at the same time.
it allows an x86 instruction to use its logical 16 registers independent of other instructions using their logical 16 registers
You neglected to point out that this allows simultaneous execution of instructions that use the same register in the compilerd code. So, if the compiler used the same register for 3 indpendent sequential operations, because it didn't think there were 'enough' registers, the CPU will effectively correct the compiler's inefficiency and use seperate OOO copies of the same register, and (depending on the operations) do the operations simultaneously, or at least overlap them.
So, you can see, the "lack of registers" does not result in an execution slowdown. ANd if you're so concerned about Opteron's 16 registers being too few, what can you say about Xeon, that only has 8! Eight 32-bit registers, I might add, and some of them have specialized usage.
only the internal Athlon (or Pentium, which also has them) can use them to assist with instructions executing out of order with respect to other instructions in a code sequence.
Yes, this is a good thing not bad!
The Athlon 64/Opteron has only 16 USEABLE registers from a programming standpoint
16 is the optimum number for Opteron and Athlon 64 because there is a low penalty for accessing L1 cache, which contains 99% of all operands. The two pipeline cycles can be filled with useful computation. When Intel eventually caves in and implements AMD64 in Pentium 5, they would definitely prefer having 32 registers because their L1 is so tiny that a larger number of registers might do some good. Unfortunately, they'll just have to bite the bullet and live with what AMD and Microsoft decided.
Petz
AI
