Advanced Micro Devices Inc (AMD)

[sgolds]

kpf, on DDR2 -

Memory is really not my field of expertise - what performance benefits are likely to be delivered with DDR-2 over DDR(-1) at the same clockrate?

Actually, clock rate is a misleading question. DDR2 is an quad pumped technology (vs. dual pumped for current DDR). It does this by using a doubled clock rate and then doing two accesses per clock. PC3200 DDR2 is internally clocked at 100MHz while PC3200 DDR1 is clocked at 200MHz.* PC3200 is the starting speed for DDR2. Some literature refers to the doubled external clock rates so this subject can get confusing. Externally, DDR2 uses 200/266/333MHz clocks, internally it uses 100/133/166MHz clocks, vs. 100/133/166/200 internal and external for DDR1.

Here are some timing diagrams explaining all this:

http://www.elpida.com/pdfs/E0294E30.pdf

The two biggest benefits are increased data throughput and reduced power consumption. DDR starts at the PC3200 level (where DDR1 ends) and goes up from there.

I think DDR2 gets its power savings from the fact it runs the internal memory cells at one half the frequency of the external bus. Thus the clock rate actual memory cells for DDR2 PC3200 equals the memory cell clock rate for DDR1 PC1600.

I understand that it is possible to make a memory controller that can use DDR or DDR2. The slots are different, so the motherboard maker would have to decide on how they want to implement it. (I don't know if both slot types can be mixed on the motherboard because the extra traces would introduce signal issues. Even if it is possible, I doubt that both types would be supported concurrently - you would have to populate one or the other.)

OTOH, if its really trivial (and doable en passant with a new stepping), why not earlier - it could help to sell a couple more FX next spring.

You mean like socket 939? That is exactly my theory. I think socket 940 will introduce DDR2 with 90nm.

*This scheme is much different from RDRAM, which uses a skewed clock. They take the clock pulse, divide it into two and put a delay loop in one of the pulses. Then they use both pulses for data access with transfers on the rising and falling edges of each pulse. RDRAM runs very hot and uses a lot of power, which is why it never got implemented in mobiles.