Advanced Micro Devices Inc (AMD)

[j3pflynn]

Dan3, correct me if I'm wrong, but I thought that was the whole concept of registered RAM, to take the direct load off the bus to allow more modules to be accessed without (necessarily) reducing speed, at the cost of a cycle of latency for the registers. If I'm understanding this correctly, I see no reason why Itanium couldn't use DDR400 if they had a chipset that could do it. Assuming, of course that the FSB side didn't have issues with it when more processors are used; if it can't handle adequate speed to make use of the increased memory bandwidth, then it'd be a waste of time to develop such an expensive MP chipset.
Paul