As Chips Scale Down, Leakage Current Goes Up. How Are Developers Responding?
April 05, 2021
All About Circuits
Scaling down the transistor to the next smallest node often sounds like a fool-proof way to improve IC performance. In reality, however, scaling introduces many hardships for IC designers. One of the most notable challenges with scaling is the increased prominence of leakage current, which significantly contributes to overall chip power consumption.
Scaling down the transistor to the next smallest node often sounds like a fool-proof way to improve IC performance. In reality, however, scaling introduces many hardships for IC designers. One of the most notable challenges with scaling is the increased prominence of leakage current, which significantly contributes to overall chip power consumption.
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Leakage?
MST can be used to reduce power consumption by lowering the leakage, just as it can be used to boost performance. Dealing with increased gate leakage at lower process geometries is one of the most difficult tasks for semiconductor designers. During third-party tests, gate leakage reductions of more than 60% were demonstrated by preventing unwanted transistor current flow in the vertical direction.
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STMicroelectronics introduced new innovations in silicon process technology that incrementally leverage existing manufacturing approaches. Fully Depleted Silicon On Insulator, or FD-SOI
FD-SOI is a planar process technology that relies on two primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top of the base silicon.
* Now STM is playing with introducing MST and looks to me may be targeting the the buried oxide layer.
