$GTCHD "Our today’s microchip’s include billions of transistors and advanced functionalities. In addition, they need to consume minimal power and operate with high performance, it’s all a matter of optimal balance between silicon area, power constraints, speed and required functionalities. As the manufacturing process is constantly getting smaller, the semiconductor’s physics introduces new geometrical, electrical and manufacturing design rule challenges, causing significantly longer project design time, and time-to- market. Our idea is to address potential design issues, early during the design phase. GBT’s team is currently working on a software tool to analyze and identify design rule violations during the IC layout construction phase. Similar to the 'spell-check' highlight concept, our tool will highlight potential violations as the designer is constructing and building the integrated circuit layout blocks. Although not a new concept, we will introduce a new approach that visually analyzes and alerts areas-of-interest associated with potential design violations. This will include graphic representation and topological recommendations within the mask layout data, where a non-compliance issue was detected. Furthermore, the system will offer an automatic correction upon the user’s approval to eliminate the flaw on the spot. The tool will be based on a region analysis concept and provide multi-zones visual feedback to increase the vitality level of the reported violations. The technology will support analog, digital and mixed IC’s design styles; including a full hierarchical support, and we predict that the technology will be mostly efficient in advanced manufacturing nodes of 7nm and below due to their acute design rule complexities. Designers will be able to design their microchips much easier, as an interactive assistance is constantly supervising them in the background, guiding them as they go, ensuring a clean-by-construction mask layout database,” said Danny Rittman, the Company’s CTO.
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