$GTCH has now filed a provisional patent application for Integrated Circuits automatic design rule correction system and method; the application number 63197635 with the U.S. Patent and Trademark Office (“USPTO”). The patent protects IP for automatic correction of manufacturing process geometrical design rules violations in microchips layout data (Professional term; DRC).
Typically, a mask layout database is created manually by a layout designer or automatically by a synthesis tool. Once the mask layout database is complete, it must go through a series of verifications in few domains. One of these checks is geometrical, to check featured dimensions according to the manufacturing process rules. Today, most of the design rule violations in the mask layout database are corrected manually by a layout designer, mainly with Analog and MIXED layout types. The designer finds each violation and manually corrects the violations by moving/modifying polygons associated with the violations. During the correction process, the layout designer may create new design rule violations and therefore the correction process may be repeated until the mask layout database does not include any design rule violations.
