$GTCH in the NEWS! As the demand for semiconductor products and features continues to grow, the industry demands advanced IC design technology in order to be able to provide affordable, smart chips, with low power consumption and high performance. Foundries (the factories that manufacturing the actual chips) are moving toward lower geometries (FinFET 7nm, 5nm and the upcoming 3nm) for fabricating next generation electronics. Designing microchips in lower geometries has become a major challenge. The geometrical/physical design rules of the tiny transistors are becoming a bottleneck when it comes to achieving reasonable chips design time. The physical limitations of the small node silicon device create steep challenges to handle and cause long and expensive IC design time. Another significant aspect is the time to market factor. Projects are taking much longer time due to complex design rules and process related constraints. This fact enforces Electronic Design Automation (“EDA”) vendors to constantly develop new solutions and approaches for the industry’s needs but they are not able to catch up with the advancements of the deep nanometer progress. As processes are moving into 7nm and below, the current physical design/verification tools do not provide sufficient performance.
ALL comments are In My Own OPINION. Please Use Your Own DD for Stock Trading.
