chipguy, I do agree that there are design complexities and latencies introduced with a floating point coprocessor. However, that wasn't the original intent of the i860. As we've discussed, the i860 was intended as a general purpose processor and later was moved to the embedded market, plus was tried as a coprocessor.
A better example would be the 287/387 chips. These were designed as math coprocessors from the git go. Times have changed since then - that approach (CPU interrupt upon hitting a float instruction, request to coprocessor) would not work because the internal clock speed of a processor has so exceeded the connect speeds between components that such an external coprocessor would be too slow to respond.
This means that ClearSpeed would need specialized software to work. Rather than servicing floating point instructions, it would need to service floating point threads. It must take an entire array-oriented task and present a completed result in memory and signal the host processor upon completion.
This is the biggest drawback to the approach, IMO. It isn't suitable for the mass Windows (or even Linux) market, but rather would make a neat coprocessor for Opteron in a supercomputer. Not a whole lot of units there!
If they provide some very easy libraries so that standard compilers can have a call interface then there is a possibility of making a game machine, either P4 or A64 based, which uses this technology as an accelerator. A similar approach can be taken with a database server, but this is an area already crowded with RISC solutions - it would be a hard market to crack. Nah, the game market is their best possibility for a mass market.
Perhaps a future X-Box?
Another issue: I tried to uncover how they are interfacing, but the white papers on their web site are vague. They have a packetized bus called ClearConnect, and my impression is that it is incompatible with anything produced by AMD or Intel. (There is a slight possibility it is HyperTransport compatible, but I doubt it.) So it needs an ASIC to translate to existing architectures, a big drawback.
This product needs more work. In its current form, I don't think a Xeon/ClearSpeed or an Opteron/ClearSpeed combo would appeal to someone considering an Itanium. That customer is more likely to compare Itanium against Power4.
Now, if ClearSpeed came up with a Socket 940 version of their chip...
AI
